Method for packaging a semiconductor device
US7344917B2 · kind B2 · utility
107Cited by
5References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2005 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Feb 9, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for packaging a semiconductor device includes forming through holes (12) in a base substrate (10) and depositing a conductive material (14) on a first side (16) of the base substrate (10) to form a conductive layer (18) such that the conductive material (14) fills the through holes (12). The conductive layer (18) is patterned and etched to form interconnect traces and pads (22). Conductive supports (24) are formed on the pads (22) such that the conductive supports (24) extend through respective ones of the through holes (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.