Metal filled through via structure for providing vertical wafer-to-wafer interconnection
US7344959B1 · kind B1 · utility
23Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2006 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Jul 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15787
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a through via connection useful in providing a vertical wafer-to-wafer interconnect structure is provided as well as the vertical interconnect structure that is formed by this method. The method of the present invention using only a metal stud for the vertical connection therefore no alpha radiation is generated by the metal stud. The method of the present invention includes an inserting step, a heating step, a thinning step and backside processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.