Multiple layer etch stop and etching method
US7344994B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2005 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Jan 30, 2026 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for etching semiconductor substrates using a deep reactive ion etching process to produce through holes or slots (hereinafter “slots”) in the substrates. The process includes applying a first layer to a back side of a substrate as a first etch stop material. The first layer is a relatively soft etch stop material. A second layer is applied to the first layer on the back side of the substrate to provide a composite etch stop layer. The second layer is a relatively hard etch stop material. The substrate is etched from a side opposite the back side of the substrate to provide a slot in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.