Stackable integrated circuit packaging
US7345361B2 · kind B2 · utility
266Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2003 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Dec 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system may include an integrated circuit die, an integrated circuit package coupled to the integrated circuit die, mold compound in contact with the integrated circuit die and the integrated circuit package, and an interconnect coupled to the integrated circuit package. A first portion of the interconnect may be in contact with the mold compound, a second portion of the interconnect might not contact the mold compound, and a third portion of the interconnect may be in contact with the integrated circuit package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.