Memory device with time-shifting based emulation of reference cells
US7345905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2006 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Aug 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of memory cells and a comparison circuit that compares a set of selected memory cells with at least one reference cell having a threshold voltage. The comparison circuit includes a bias circuit that applies a biasing voltage having a substantially monotone time pattern to the selected memory cells and to the at least one reference cell, sense amplifiers that detect the reaching of a comparison current by a cell current of each selected memory cell and by a reference current of each reference cell, a logic unit that determines a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding cell current and by the at least one reference current, and a time shift structure that time shifts at least one of said detections according to at least one predefined interval to emulate the comparison with at least one further reference cell having a further threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.