Inventor · Fiorano al Serio, IT

Efrem Bolandrina

34Patents
5h-index
17Co-inventors
66Inventor score

Filing activity: Jun 4, 2004 → Mar 29, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US7554861B2 Memory device with a ramp-like voltage biasing structure and reduced number of reference cells Physics 45 Active
US7345905B2 Memory device with time-shifting based emulation of reference cells Physics 37 Active
US7272059B2 Sensing circuit for a semiconductor memory Physics 13 Expired
US10692557B1 Reference voltage management Physics 5 Active
US9025392B1 Memory device with reduced neighbor memory cell disturbance Physics 5 Active
US9418735B2 Memory device with reduced neighbor memory cell disturbance Physics 3 Active
US7965561B2 Row selector occupying a reduced device area for semiconductor memory devices Physics 3 Active
US10762944B2 Single plate configuration and memory array operation Physics 2 Active
US8730754B2 Memory apparatus and system with shared wordline decoder Physics 2 Active
US10083744B2 Memory device with reduced neighbor memory cell disturbance Physics 2 Active
US11626151B2 Single plate configuration and memory array operation Physics 2 Active
US9767898B2 Memory device with reduced neighbor memory cell disturbance Physics 2 Active
US7006025B2 Method for generating a reference current for sense amplifiers and corresponding generator Physics 1 Expired
US8159899B2 Wordline driver for memory Physics 1 Active
US11967372B2 Shared decoder architecture for three-dimensional memory arrays Physics 1 Active
US11545219B2 Memory device with single transistor drivers and methods to operate the memory device Physics 1 Active
US11915740B2 Parallel access in a memory array Physics 1 Active
US10916288B1 Sensing techniques for a memory cell Physics 1 Active
US12183421B2 Techniques for indicating row activation Physics 0 Active
US11289147B2 Sensing techniques for a memory cell Physics 0 Active
US11682439B2 Parallel access for memory subarrays Physics 0 Active
US12249362B2 Single plate configuration and memory array operation Physics 0 Active
US12260907B2 Shared decoder architecture for three-dimensional memory arrays Physics 0 Active
US11217293B2 Reference voltage management Physics 0 Active
US11877457B2 Vertical 3D memory device and accessing method Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.