Apparatus and method for implementing programmable levels of error severity
US7346812B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 27, 2000 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | Sep 4, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0781
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus using a set of registers for indicating multiple error levels in a data processing system, wherein a register allows software to reprogram or redefine the error level to another desired error level. One embodiment of the invention involves a method for indicating errors in a data processing system with multiple error levels, indicating that an error corresponds to one of the multiple error levels, representing the error with a set of memory cells, and changing the error level of the error to another error level of the multiple error levels. A second embodiment of the invention involves a data processing system or an error log system, having an associated error level chosen from a plurality of error levels for an error. The data processing system or error log system includes a set of memory cells, with a primary error log to record the error, at least one error enable register that can be read and written to redefine the error level of the error to one of said plurality of error levels. In a preferred embodiment, the recording of the error levels with the set of memory cells includes recording the first occurrence of the most severe error in the primary error …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.