Through-core self-test with multiple loopbacks
US7346819B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2004 |
| Grant date | Mar 18, 2008 |
| Priority date | — |
| Expiry date | May 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31813
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the test sequence generator and is configured in a loopback mode to transmit and receive the test data sequence. The second transceiver receives the test data sequence received by the first transceiver and is configured in a loopback mode to transmit and receive the test data sequence. The test sequence analyzer determines whether the test data sequence received by the second transceiver matches the test data sequence generated by the test sequence generator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.