Post bump passivation for soft error protection
US7348210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2005 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Apr 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15787
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top surface and on the electrically conducting bond pad, wherein the first passivation layer comprises a first hole directly above the electrically conducting bond pad, and (iv) an electrically conducting solder bump filling the first hole and electrically coupled to the electrically conducting bond pad; and (b) forming a second passivation layer on the first passivation layer, wherein second passivation layer is in direct physical contact with the electrically conducting solder bump, and wherein the electrically conducting solder bump is exposed to a surrounding ambient immediately after said forming the second passivation layer is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.