Methods of fabricating semiconductor device using sacrificial layer
US7348277B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2006 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Feb 13, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There are provided methods of fabricating a semiconductor device using a sacrificial layer. The methods provide an approach to maintaining thickness distribution of the interlayer insulating layers below a sacrificial layer uniform on an overall surface of a semiconductor substrate during performing a chemical mechanical polishing (CMP) process in a damascene process. To this end, the method includes forming a pad layer, a pad interlayer insulating layer, an etch stop layer pattern, a planarized interlayer insulating layer and a sacrificial layer sequentially on a semiconductor substrate. At least one trench is formed in the sacrificial layer and the planarized interlayer insulating layer. A via contact hole is formed in the etch stop layer pattern, the pad interlayer insulating layer, and the pad layer to be disposed below the trench. A diffusion barrier layer and a conductive layer are sequentially formed to fill the trench and the via contact hole. A CMP process is performed on the conductive layer, the diffusion barrier layer, and the sacrificial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.