Vertical channel semiconductor devices and methods of manufacturing the same
US7348628B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2006 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Jun 7, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.