Dynamically coupled metrology and lithography
US7349752B1 · kind B1 · utility
8Cited by
4References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2004 |
| Grant date | Mar 25, 2008 |
| Priority date | — |
| Expiry date | Feb 26, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for determining tolerances are disclosed that can be used for determining whether a lot of semiconductor wafers needs to be reworked. Overlay tolerance, critical dimension tolerance and a dynamic line edge placement tolerance are determined using error measurements that are taken from sample wafers in the lot, giving tolerances that reflect the error state of that particular lot of semiconductor wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.