Patent · US Expired

Data synchronization arrangement

US7350092B2 · kind B2 · utility

3Cited by

6References

11Claims

0Family size

Assignee

TEXAS INSTRUMENTS DEUTSCHLAND GMBH · DE

Inventors

Norbert Reichel · Wartenberg, DE
Joerg Goller · Ramstein-Miesenbach, DE

Key dates

Filing date	Mar 8, 2005
Grant date	Mar 25, 2008
Priority date	—
Expiry date	Dec 22, 2025

Classification

Technology area (CPC H)Electricity
CPC primaryH04L7/005
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A data synchronization arrangement is provided for exchanging clocked data between different clock domains running at the same clock frequency but at an arbitrary relative phase shift. An input data stream synchronized in the first clock domain is written into respective locations of a buffer memory through a write select multiplexer under control of a write select shift register clocked by the first domain clock. An output data stream synchronized in the second clock domain is read from the respective locations of the buffer memory through a real select multiplexer under control of a read select shift register clocked by the second domain clock. A bit synchronization circuit is provided for loading the read select shift register with a bit pattern that has a relative offset relative to the bit pattern of the write select shift register, to correlate for the difference in clock phases.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.