Method for wafer level package of sensor chip
US7351609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2006 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Oct 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for wafer level package (WLP) of sensor chips is provided, including the steps of: providing a wafer, the wafer including a plurality of die regions, each the die region on a first surface of the wafer comprising an active area and a pad surrounding the active area; bounding a transparent protective layer to the first surface of the wafer; forming a stress buffer on a second surface of the wafer; using etching or laser drill to form a via hole at the location between two neighboring die regions through the stress buffer and the wafer to expose the pad or a conductive line between two neighboring pads; and forming a plurality of bump electrodes on the stress buffer for electrical connection to the pads through the via holes. The method can prevent pollution of the die, improve the convenience of package, reduce the manufacture cost, increase the package reliability, and solve the stress problem caused by attaching the die directly to the PCB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.