Method of editing a semiconductor die
US7352001B1 · kind B1 · utility
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14References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2006 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Jul 14, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Resistance and capacitance are added to a prototype die to fix or identify performance issues with the integrated circuit formed in the die by forming a thin piece of silicon on the top surface of the die. For resistance, vias are formed to regions on the metal traces and to opposite ends of the piece of silicon using a FIB system. For capacitance, a dielectric is formed on the piece of silicon, and a layer of metal is formed on the dielectric. Vias are formed to regions on the metal traces, to the piece of silicon, and to the layer of metal using the FIB system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.