Twin MONOS array for high speed application
US7352033B2 · kind B2 · utility
5Cited by
12References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2005 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Dec 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a metal bit structure of Twin MONOS memory cell with large channel width and its operational method for high-speed applications using a metal bit array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.