Methods for a multiple die integrated circuit package
US7352058B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 1, 2005 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Dec 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4084
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for a multiple die package for integrated circuits are disclosed. An insulator layer is provided and one or more vias are formed within it. The insulator may be provided without vias, and vias formed later. At least one integrated circuit is provided and electrically coupled to at least one lead of a first leadframe overlying one surface of the insulator. At least one second integrated circuit is provided and electrically coupled to a second leadframe overlying a second surface of the insulator. Electrical connections between the two leadframes and the first and second integrated circuits are made through the insulator at selected locations, by coupling at least one lead of the first and second leadframes one to another. The leads of the first and second leadframe may be physically coupled by a welding process within vias in the insulator. A method for a removable storage card is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.