Semiconductor memory device and method of arranging a decoupling capacitor thereof
US7352646B2 · kind B2 · utility
1Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2004 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Dec 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device with improved operational performance by reducing the level variation of first and second power voltages applied to a sense amplifier by efficiently locating a decoupling capacitor. The decoupling capacitor is arranged on an empty region of a plurality of the first and second sense amplifiers and connected between the first and second power voltage lines. A plurality of global data I/O line pairs is arranged perpendicular to the direction of a plurality of local data I/O line pairs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.