Method for analyzing circuit pattern defects and a system thereof
US7352890B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2006 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Feb 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for analyzing defects in electronic circuit patterns, including: comparing position information of structural defects with position information of electrical faults and extracting corroborated defects having common position information between the structural defects and electrical faults; classifying images of extracted corroborated defects into critical defect images and non-critical defect images based on a pre-stored classification rule which defines critical and non-critical defects by referring to images of defects, position information of defects, and results of performing an electronic test; modifying the pre-stored classification rule by correcting classification of classified defect images displayed on the screen; and repeating the operations for each subsequent object, wherein for each present object under inspection, using a modified pre-stored classification rule with respect to a previous object, as the pre-stored classification rule for the operations with respect to the present object.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.