Method of switching external models in an automated system-on-chip integrated circuit design verification system
US7353156B2 · kind B2 · utility
2Cited by
4References
10Claims
0Family size
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Key dates
| Filing date | Feb 1, 2002 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Oct 1, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.