System and method for re-routing signals between memory system components
US7353316B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 24, 2006 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Jul 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of memory modules used in a computer system each include a memory hub that is connected to a plurality of memory devices. The memory modules are connected to each other in series so that signals are coupled between the memory modules and the memory hub controller through any intervening memory modules. The signals are coupled to and from the memory modules through high-speed bit-lanes. In the a bit-lane connected to any of the memory hubs is inoperative, the memory hub re-routes signals that would be coupled through the inoperative bit-lane to an adjacent bit lane. When the signal reaches a memory hub in which the bit-lane is no longer inoperative, the memory hub routes the signal back to the original bit lane. In this manner, multiple bit-lane failures can be accommodated using a signal extra bit-lane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.