Multicore processor test method
US7353440B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2004 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Feb 24, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/267
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In processors having multiple cores, such as CMPs, an independent MISR test pattern compression circuit is provided for each logic block, which makes it possible to perform LSI tests more efficiently. A processor includes a plurality of logic block circuits, which include at least a first processor core circuit and a second processor core circuit, each processor core circuit having a scan chain circuit and being operable independently, and a common block circuit having a scan chain circuit and a cache circuit that is shared by the first processor core circuits and the second processor core circuits. The processor further includes, for each logic block, a test pattern generating circuit operable to generate a test pattern and input the test pattern to the scan chain of each logic block circuit, and a test pattern compression circuit operable to accept as input and compress the test pattern output by the scan chain of each logic block circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.