Method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance
US7353471B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2005 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Dec 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductivity is disclosed. One embodiment of a novel method for analyzing the conductivity of a semiconductor chip design that comprises a plurality of physical layers includes defining at least one thermal layer within the plurality of physical layers, where the thermal layer(s) represents a variance in thermal conductivity relative to a remainder of the semiconductor chip design, and computing a thermal conductivity of the thermal layer(s). As the thermal layer(s) represents variances in thermal conductivity over the semiconductor chip design, the thermal layer(s) does not necessarily correspond one-to-one to the physical layers of the semiconductor chip design. Thus, the thermal conductivities within the semiconductor chip design can be computed from the thermal layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.