Power network synthesizer for an integrated circuit design
US7353490B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2004 |
| Grant date | Apr 1, 2008 |
| Priority date | — |
| Expiry date | Apr 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plan for a power network for an integrated circuit device is automatically preparing in two stages. In a first stage, a number of simplified plans are prepared on a global scale, without regard to design rule checking constraints and routing blockages. Next, the simplified plans are evaluated to select a plan that conforms to a user-specified limit for an attribute, such as maximum voltage drop. The selected simplified plan, which identifies a total count of power wires and a width of the power wires, is used in a second stage to prepare a more detailed plan that honors the design rule checking constraints and routing blockages. The detailed plan is evaluated to check for conformance with the user-specified limit on the attribute, and if necessary the detailed plan is changed, e.g. by increasing wire width one or more times, to achieve conformance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.