Topography compensated film application methods
US7354779B2 · kind B2 · utility
1Cited by
7References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2006 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | May 19, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0276
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for applying topographically compensated film in a semiconductor wafer fabrication process are disclosed. The processes include premapping a surface of a wafer so as to determine the local topography (e.g., z-height) of the wafer and then applying a variable depth of a film to the wafer, such that the variable depth is modulated based on the local topography of the wafer. The resultant topography of the applied film and wafer is substantially planar (e.g., within approximately 100 nm) across the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.