Three-dimensional device fabrication method
US7354798B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Jan 2, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is described for fabricating a three-dimensional integrated device including a plurality of vertically stacked and interconnected wafers. Wafers (1, 2, 3) are bonded together using bonding layers (26, 36) of thermoplastic material such as polyimide; electrical connections are realized by vias (12, 22) in the wafers connected to studs (27, 37). The studs connect to openings (13, 23) having a lateral dimension larger than that of the vias at the front surfaces of the wafers. Furthermore, the vias in the respective wafers need not extend vertically from the front surface to the back surface of the wafers. A conducting body (102) provided in the wafer beneath the device region and extending laterally, may connect the via with the matallized opening (103) in the back surface. Accordingly, the conducting path through the wafer may be led underneath the devices thereof. Additional connections may be made between openings (113) and studs (127) to form vertical heat conduction pathways between the wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.