Fabrication method for single and dual gate spacers on a semiconductor device
US7354837B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 2005 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Apr 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
Abstract
A fabrication method for a semiconductor device is provided. A substrate has an array area with a first gate and a peripheral area with a second gate. First and second isolation layers made of different materials are sequentially formed to cover the first gate, the second gate and the substrate. A portion of the second isolation layer is removed to form spacers on sidewalls of the first and second gates and expose the first isolation layer on a top of the first gate, a top of the second gate, and a surface of the substrate. The spacers on the first isolation layer in the array area are removed. The first isolation layer on the top of the first gate and the surface of the substrate is removed, thereby leaving a portion of the first isolation layer covering on the sidewalls of the first gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.