Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array

US7355230B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Andreas Thies · Tirschenreuth, DE
• Klaus Muemmler · Dresden, DE

Key dates

• Filing date: Nov 30, 2004
• Grant date: Apr 8, 2008
• Expiry date: Oct 24, 2025

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/905
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.