Diffusion topography engineering for high performance CMOS fabrication
US7355262B2 · kind B2 · utility
21Cited by
11References
16Claims
0Family size
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Key dates
| Filing date | Mar 17, 2006 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | May 3, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on the semiconductor substrate, and forming a MOS device in the diffusion region. The DTE causes silicon migration, forming a rounded or a T-shaped surface of the diffusion regions. The method may further include recessing a portion of the diffusion region before performing the DTE. The diffusion region has a slanted surface after performing the DTE.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.