Apparatus and method for controlling a delay- or phase-locked loop as a function of loop frequency
US7355464B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 9, 2005 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Jul 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows maximum tracking bandwidth, regardless of process, voltage, or temperature variations. Central to the technique is to effectively operate the loop at a lower frequency close to its own intrinsic bandwidth (1/tLoop) instead of at the higher frequency of the clock signal (1/tCK). To do so, in one embodiment, the loop delay, tLoop, is measured or estimated prior to operation of the loop. The phase detector is then enabled to operate close to the loop frequency, 1/tLoop. In short, the phase detector is made not to see activity during useless delay times, which prevents the loop from overreacting and becoming unstable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.