Surrogate stencil buffer clearing
US7355602B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2004 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Mar 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T11/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for effectively clearing stencil buffers at high speed using surrogate stencil buffer clearing. A hardware register tracks the number of surrogate clears of the stencil buffer since the last actual clear. Bits are reserved in each stencil register for storing the surrogate clear number that cleared other stencil registers the last time the stencil register held an assigned value. A comparison between the contents of the hardware register and the reserved bits in each stencil register determines if each stencil register should be assigned a cleared value. If the numbers do not match the stencil register is assigned a predetermined surrogate clear value. In some applications the number of reserved bits is fixed, while in other applications the number of reserved bits can be set, either by a designer or by software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.