Memory array with global bitline domino read/write scheme
US7355881B1 · kind B1 · utility
8Cited by
8References
10Claims
0Family size
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Key dates
| Filing date | Nov 22, 2005 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Feb 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.