Method of programming, erasing and reading memory cells in a resistive memory array
US7355886B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2006 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Dec 5, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/72
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present approach is a method of writing (which may be programming or erasing) data to a selected memory cell of a memory array. The array includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells each including a diode and a resistive memory device in series connecting a word line and a bit line, and a plurality of transistors, each having a first and second source/drain terminals and a gate, each transistor having a first source/drain terminal connected to a bit line. In the present method a voltage is applied to a selected word line, and a voltage is applied to the second source/drain terminal of a transistor having its first source/drain terminal connected to a selected bit line. The voltage applied to the selected word line is greater than the voltage applied to the second source/drain terminal of that transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.