Synchronous output buffer, synchronous memory device and method of testing access time
US7355901B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2006 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Apr 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An output buffer includes an output terminal, a pull up module, a pull down module and an output latching module. The pull up module pulls up the output terminal to a first source voltage when the pull up module is active. The pull down module pulls down the output terminal to a second source voltage when the pull down module is active. The output latching module latches a data signal in response to a state of an output clock signal in a first operation mode. The output latching module latches the data signal in response to a leading edge of the output clock signal in a second operation mode. The output latching module drives the pull up module and the pull down module in response to the data signal latched by the output latching module, so that the output latching module outputs the data signal to the output terminal in a second operation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.