System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form
US7356673B2 · kind B2 · utility
8Cited by
17References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2001 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Nov 13, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is provided for processing a first instruction set and a second instruction set in a single processor. The method includes storing a plurality of instructions of the second instruction set in a plurality of buffers proximate to a plurality of execution units, executing an instruction of the first instruction set in response to a first counter, and executing at least one instruction of the second instruction set in response to at least a second counter, wherein the second counter is invoked by a branch instruction of the first instruction set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.