Dummy fill for integrated circuits
US7356783B2 · kind B2 · utility
31Cited by
57References
73Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2004 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Apr 30, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.