Optimizing IC clock structures by minimizing clock uncertainty
US7356785B2 · kind B2 · utility
9Cited by
41References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2006 |
| Grant date | Apr 8, 2008 |
| Priority date | — |
| Expiry date | Sep 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3016
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a set of second buffers so each leaf is driven by an inserted buffer without timing violations, and moving the first buffer to a center of gravity of the set of second buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.