Method for forming a FinFET by a damascene process
US7358142B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2005 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Jan 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/024
Abstract
A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.