Relaxed, low-defect SGOI for strained Si CMOS applications
US7358166B2 · kind B2 · utility
50Cited by
8References
23Claims
0Family size
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Key dates
| Filing date | Aug 19, 2005 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Dec 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.