Process for fabricating a semiconductor package and semiconductor package with leadframe
US7358598B2 · kind B2 · utility
2Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2004 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | May 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a flat metal leadframe including spaced apart portions, at least some of which constitute electrical connection leads. A filling material fills the spaces that separate the spaced apart portions of the leadframe to form a plate before fastening an integrated circuit chip to the front of the leadframe. Electrical connections are made between the chip and the electrical connection leads. The chip is then encapsulated on the front of the leadframe using a formed or attached encapsulant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.