Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes
US7358761B1 · kind B1 · utility
56Cited by
10References
23Claims
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Key dates
| Filing date | Jan 21, 2005 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Jan 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1737
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on to create correct selection. Using such structure, larger multiplexer, including priority multiplexers, tristate buses or larger look-up tables (LUTs) can be created. These novel structures can implement priority, non-priority or tristate multiplexers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.