Memory repair system and method
US7359261B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2006 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Feb 7, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/789
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An IC includes a memory module that stores at least one of data and code. A memory repair database stores data relating to defective memory addresses. A memory control module communicates with the memory module and the memory repair database, detects defective memory locations in the memory module, locates redundant memory elements in the memory module, stores information that associates memory addresses of the defective memory locations with the redundant memory elements in the memory repair database, and outputs the information. The memory control module includes a plurality of electrical fuses. Storing the information includes electrically altering at least one of the plurality of electrical fuses. A redundant memory decoder module receives the information and physically remaps the memory addresses to the redundant memory locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.