Layout structure for sub word line drivers and method thereof
US7359280B2 · kind B2 · utility
3Cited by
3References
29Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 23, 2006 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Sep 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/998
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout structure for sub word line drivers and method thereof. The example layout structure may include at least one N-channel transistor arrangement having a cross sectional width and a cross sectional length, the N-channel transistor arrangement oriented such that the cross sectional length extends along a first direction, the first direction oriented along a sub word line driver from a first sub array block to a second sub array block. The example method may arrange the at least one N-channel transistor between the first and second sub array blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.