Enforcing global ordering through a caching bridge in a multicore multiprocessor system
US7360008B2 · kind B2 · utility
4Cited by
18References
25Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 30, 2004 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Jul 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the system interconnect, processor requests, and processor request completions may trigger corresponding snooping transactions and request completions to the cores. The order in which the transactions are observed on the system interconnect may impose the order in which the transaction triggered to the core are generated. Since this ordering is between multiple interfaces this is referred to as global ordering.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.