Hierarchical virtual model of a cache hierarchy in a multiprocessor system
US7360033B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2006 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Jun 5, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/2542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.