Variable width alignment engine for aligning instructions based on transition between buffers
US7360059B2 · kind B2 · utility
0Cited by
10References
18Claims
0Family size
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Key dates
| Filing date | Feb 3, 2006 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Apr 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. The beginning of a second instruction is determined based on the size of the first instruction. The size of the second instruction is decoded and the processor determines whether loading the second instruction will deplete one of the plurality of buffers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.