Patent · US Expired

Use of models in integrated circuit fabrication

US7360179B2 · kind B2 · utility

222Cited by

57References

75Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Taber H. Smith · San Jose, US
Vikas Mehrotra · London, GB
David White · San Jose, US

Key dates

Filing date	May 31, 2005
Grant date	Apr 15, 2008
Priority date	—
Expiry date	May 31, 2025

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02P90/02
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.