Method and apparatus for performing retiming on field programmable gate arrays
US7360190B1 · kind B1 · utility
19Cited by
6References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2004 |
| Grant date | Apr 15, 2008 |
| Priority date | — |
| Expiry date | Oct 3, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying registers on near-critical paths. The registers are moved to shorten lengths of one or more near-critical paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.