Gabriel Quan
17Patents
8h-index
23Co-inventors
68Inventor score
Filing activity: May 31, 2002 → Apr 27, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6779169B1 | Method and apparatus for placement of components onto programmable logic devices | Physics | 26 | Expired |
| US9569574B1 | Method and apparatus for performing fast incremental physical design optimization | Physics | 22 | Active |
| US7669157B1 | Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches | Physics | 20 | Active |
| US7257800B1 | Method and apparatus for performing logic replication in field programmable gate arrays | Physics | 20 | Expired |
| US7360190B1 | Method and apparatus for performing retiming on field programmable gate arrays | Physics | 19 | Expired |
| US7194720B1 | Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices | Physics | 12 | Expired |
| US7464362B1 | Method and apparatus for performing incremental compilation | Physics | 8 | Active |
| US7181717B1 | Method and apparatus for placement of components onto programmable logic devices | Physics | 8 | Expired |
| US7594204B1 | Method and apparatus for performing layout-driven optimizations on field programmable gate arrays | Physics | 6 | Expired |
| US8589849B1 | Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices | Physics | 4 | Active |
| US8250505B1 | Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches | Physics | 4 | Active |
| US8434044B1 | Specifying placement and routing constraints for security and redundancy | Physics | 2 | Active |
| US8589838B1 | M/A for performing incremental compilation using top-down and bottom-up design approaches | Physics | 1 | Active |
| US11093672B2 | Method and apparatus for performing fast incremental physical design optimization | Physics | 1 | Active |
| US9122826B1 | Method and apparatus for performing compilation using multiple design flows | Physics | 0 | Active |
| US10635772B1 | Method and apparatus for performing fast incremental physical design optimization | Physics | 0 | Active |
| US9754065B2 | Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.