Field effect transistor with buried gate pattern
US7361545B2 · kind B2 · utility
16Cited by
0References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2005 |
| Grant date | Apr 22, 2008 |
| Priority date | — |
| Expiry date | Jun 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/711
Abstract
A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.